define the terms fan-out and noise margin and derive a

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TASK INTRODUCTION

You have completed your engineering apprenticeship and have a position in the design department of your company. You have been asked by your line manager, Mithun, to produce a combinational logic circuit (Task 2). For Task 3 you have been requested to evaluate the operation of JK Flip Flops and present your findings and measurements to your line manager.

TASK 1:

a) Using Manufacturer's datasheets complete the table below using Nominal values for the logic families.

 

LS TTL

ALS TTL

CMOS

HCMOS

VIL

 

 

 

 

VIH

 

 

 

 

AIL

 

 

 

 

IIH

 

 

 

 

VOL

 

 

 

 

VOH

 

 

 

 

COL

 

 

 

 

LOH

 

 

 

 

Fan-out

 

 

 

 

Noise Margin

 

 

 

 

b) Define the terms Fan-out and Noise Margin.

TASK 2:

Design a circuit whose output goes HIGH when its inputs are. A is high and B is low and either input C or input D is also HIGH

Procedure:
a) Derive a Boolean that describes the performance of the required circuit.
b) Rearrange the expression in Sum-of-Products (SOP) form.
c) Using simulation software, Draw the circuit diagram and simulate its operation.
d) Produce a four-variable truth table and apply all combinations of input variables to the circuit and each time note the logical state.
e) Demonstrate the circuit operation to your tutor.

A

B

C

D

F

0

0

0

0

 

0

0

0

1

 

0

0

1

0

 

0

0

1

1

 

0

1

0

0

 

0

1

0

1

 

0

1

1

0

 

0

1

1

1

 

1

0

0

0

 

1

0

0

1

 

1

0

1

0

 

1

0

1

1

 

1

1

0

0

 

1

1

0

1

 

1

1

1

0

 

1

1

1

1

 

Opportunity for Distinction (Part A) (Both Part A and Part B must be completed for D2) Demonstrate, with photographic evidence, that you have simulated the circuit in Task 2 without any help from your peers and/or tutor. D2

Opportunity for Merit

Use Karnaugh Maps to check the SOP found in Part b, is equivalent to the original Boolean expression. found in Part a. M2

TASK 3:

a) Design a 4 bit asynchronous counter using JK flip flops to count between 2 and 9.
Your design must include:
- Flow diagram
- Sequence table
- Karnaugh maps

b) Using a Logic Tutor or Multisim, construct the counter and demonstrate to your Tutor.

Opportunity for Merit

Produce a report containing the information found for TASKs 2 and 3. You will need to use a variety of word processing features and circuit diagrams created in Multisim. You will also need to use engineering language correctly. M3 Opportunity for Distinction (Part B) (Both Part A and Part B must be completed for D2) Demonstrate, with photographic evidence, that you have built the circuit in Task 3 without any help from your peers and/or tutor. D

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