1. Design and draw a ladder diagram circuit suitable for a PLC which will fulfil the following control requirement:

A momentary push switch is to be recognised, remembered and used to switch on an output for a period of 30 seconds. After 30 seconds this output is to be switched off and must be off for 0.5 seconds before a second output switches on.

The second output remains on until a second push switch is operated to turn it off. If the second push is operated at any time then the current output must turn off and the system await the press of the first push. The rungs of the ladder diagram must contain interlock contacts which prevent both outputs being on at the same time.

2. Redesign and improve the pelican crossing ladder diagram given of FIGURE 1 of lesson PLC - 6 - 2 by adding timer rungs and counter rungs between rungs 12 and 14 (or any similar workable scheme) together with the necessary contacts inserted in the amber and green man lights of rungs 7 and 10, etc. The chart below shows the required sequence of events. Note that a section of the chart is repeated a total of 16 times. The time intervals are given below.

Time period 1 is the 'normal' conditions.

Time period 2 is after the pedestrian presses the push button.

The change from period 2 to period 3 can only be made after at least one five second check of the road sensors.

The time interval between 3 and 4 is 4 seconds.

The time interval between 4 and 5 is 10 seconds.

The time interval between 5 and 6 is 0.5 seconds.

The time interval between 6 and 7 is 0.5 seconds.

It is not necessary to show the whole of the traffic light ladder diagram of lesson PLC - 6 - 2, only rungs which have been modified.

There must, however, be a comprehensive explanation of the operation of the modified rungs accompanying the modified ladder diagram.

3. The chart below shows a required set of step sequences with the same time interval between steps.

Provide a ladder diagram and a comprehensive explanation as a solution for this chart by using two eight-bit shift registers (SFT0 controls relays 50 to 57, SFT1 controls relays 60 to 66). The sequence is to have an initial start signal and thereafter can be free running. A reset control and timer to clock the shift registers must be provided.

4. (a) An A/D conversion circuit with 10 bit resolution has an input range of 0 - 5 V. A second has a 12 bit resolution and an input range of 0 - 10 V. Calculate the digital output value that will represent a 2 V input for both of the A/D converters. Convert the digital levels in both cases to hexadecimal and then to binary values.

(b) Explain briefly from what you notice about the digital output values in (a) why a digital output value of an A/D converter is rarely the exact same digital value as the analogue input value.

(c) State briefly why a PLC A/D module haveing 4 analogue input channels would probably not incorporate 4 internal A/D circuits.

(d) State briefly which of the two digital output values in (a) is the more accurate and why.

5. Explain briefly the technique of multiplexed switching of analogue signals.

6. The diagram of FIGURE 1 shows a 3 input R/2R digital to analogue converter circuit. By working back from the output (or otherwise) to find the equivalent input resistance in order to determine the input voltage, show that the output voltage values for the following digital input combinations are as shown below.

7. State briefly: (i) what is meant by a LAN (ii) types of LAN (iii) an application of LANs (iv) the types of cable likely to be used in a LAN (v) the meaning of RTU (vi) what the current title of EIA-422 is and to what it relates (vii) to what the protocal IEEE-488 relates.